1. Field of the Invention
The invention relates to a frequency comparator, and in particular to a frequency comparator utilizing a phase-frequency detector.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional frequency comparator 100. The frequency comparator 100 is used to compare frequencies of an in-phase clock signal CLKI and a reference clock signal CLKR. As shown in the figure, in the frequency comparator 100, three D-flip flops D1, D3 and D5 are connected in series, wherein a data input D and a clock input CK of the D-flip flop D1 respectively receiving CLKI and CLKR. Similarly, three D-flip flops D2, D4 and D6 are connected in series, wherein a data input D and a clock input CK of the D-fip flop D2 respectively receiving a quadrature clock signal CLKQ and the reference clock signal CLKR. The in-phase clock signal CLKI and the quadrature CLKQ have the same frequency but differ 90 degrees in phase. At every transition of the reference clock signal CLKR, the D-flip flops D1 and D2 sample the in-phase clock signal CLKI and the quadrature clock signal CLKQ respectively, and the D flip-flops D3-D6 serve as registers to save the sampled results of the D-flip flops D1 and D2. A logic circuit 12 receives output signals Q3-Q6 and inverted output signals Q3b-Q6b of the D-flops D3-D6, where Q3b-Q6b denote inverse signals of the output signals Q3-Q6 respectively, and outputs an up signal F_up and a down signal F_dn representative of the frequency comparison result of CLKI and CLKR.
FIG. 2A and 2B are timing diagrams of the reference clock signal CLKR, the in-phase clock signal CLKI, and the quadrature clock signal CLKQ in cases where the frequency of CLKI (or CLKQ ) is lower and higher than that of CLKR respectively. Referring to FIG. 2A, it is shown that (CLKI, CLKQ) changes as: (1,0)→(0, 0)→(0, 1)→(1, 1)→(1, 0) . . . , and so forth. Similarly, turning to FIG. 2B, it is shown that (CLKI, CLKQ) changes as: (1, 1)→(0, 1)→(0, 0)→(1, 0)→(1,1).
FIG. 3 is a truth table of the logic circuit 12 of FIG. 1. Thus, according to the truth table, when the up signal F_up is high and the down signal F_dn is low, the frequency of the in-phase clock signal CLKI (or the quadrature clock signal CLKQ) is beyond that of the reference clock signal CLKR. Conversely, when F_up is low and F_dn is high, the frequency of CLKI (or CLKQ ) is below that of CLKR.
However, the difference between frequencies of the in-phase clock signal CLKI and the reference clock signal CLKR is limited to a medium range for accurate comparison result based on the truth table of FIG. 3. Resultingly, this limits applications of the frequency comparator 100.